1. Field of the Invention
This invention relates to a pattern layout used for manufacturing semiconductor devices and more particularly to a pattern layout of an integrated circuit having a uniformly repeated fine pattern of lines and spaces. Further, this invention relates to a correction method of an integrated circuit pattern layout and a NAND flash memory.
2. Description of the Related Art
In a NAND flash memory, a uniformly repeated pattern of lines and spaces drawn based on a design rule with the size approximately equal to the limit of the resolution is used to form control gate wires of the memory cell portion. The pattern of the integrated circuit is exposed by use of a photomask. In the exposure process for the memory cell portion by use of the photomask, there occurs a problem that the resolution of the boundary portion of the end portion of the memory cell portion is lowered although the resolution of the uniformly repeated area of the central portion of the memory cell portion is high.
In order to solve the above problem, a method is proposed to arrange an auxiliary pattern or dummy pattern to maintain the uniform repetitiveness on the photomask in addition to the original pattern (Jpn. Pat. Appln. KOKAI Publication No. 2006-293081). With the above method, for example, in order to preferably form a design pattern of the end portion of the memory cell portion on the wafer, the dimensions of the mask are corrected or the auxiliary pattern is arranged on the wafer to make the design pattern dimensions equal to the resist pattern dimensions.
However, even if this type of mask is used, a lowering in the optical contrast in a portion near the end portion of the memory cell portion of lines and spaces and a lowering in the lithography margin cannot be sufficiently suppressed at present.
Thus, conventionally, in the line and space pattern of the memory cell portion of the NAND flash memory or the like, there occurs a problem that the resolution of the end portion is lowered at the pattern exposure time and the lithography margin is lowered. Further, even when the auxiliary pattern or dummy pattern used to maintain the uniform repetitiveness is arranged on the exposure mask, it is difficult to attain sufficiently high resolution.